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Restadores

1. Códigos

sub.v
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module sub #(
  parameter Width = 32
) (
  input  signed [Width-1:0] a_i,
  input  signed [Width-1:0] b_i,
  output signed [Width-1:0] sub_o
);

  assign sub_o = a_i - b_i;     

endmodule
sub_reg.v
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module sub_reg #(
  parameter Width = 32
) (
  input                         rst_i,
  input                         clk_i,
  input      signed [Width-1:0] a_i,
  input      signed [Width-1:0] b_i,
  output reg signed [Width-1:0] sub_o
);

  wire [Width-1:0] sub_w;
  assign sub_w = a_i - b_i; 

  always @(posedge clk_i, posedge rst_i) begin
    if (rst_i) begin 
      sub_o <= 0;
    end else begin
      sub_o <= sub_w;
    end
  end  

endmodule

2. Verificación

adder_tb.v
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`timescale 1ns / 100ps    
`include "sub.v"

module sub_tb #(
  parameter Width = 32 
) ();

  // Definición de señales de entrada y salida
  reg [Width-1:0] a;
  reg [Width-1:0] b;

  wire [Width-1:0] c;

  // Instanciacion del modulo
  sub #(Width) DUT (
    .a_i(a),
    .b_i(b),
    .sub_o(c)
  );

  // Abrir archivo de salida
  integer write_data;
  localparam SF = 2.0**-21.0;
  time t;

  // Estimulo de las entradas
  initial begin
    write_data = $fopen("sub_tb_output.txt","w");
    $dumpfile("sub_tb.vcd");
    $dumpvars(0,sub_tb);
    $timeformat(-9, 2, " ns", 10);
    a = 32'b00000000001000000000000000000000; //  1.0
    b = 32'b00000000001000000000000000000000; //  1.0;
    #100; t = $time;
    $fdisplay(write_data, "Tiempo: %t\ta = %10.7f\tb = %10.7f\tc = %10.7f",t,$itor(a)*SF,$itor(b)*SF,$itor(c)*SF);

    a = 32'b00000000001100000000000000000000; //  1.5
    b = 32'b00000000001100000000000000000000; //  1.5;
    #100; t = $time;
    $fdisplay(write_data, "Tiempo: %t\ta = %10.7f\tb = %10.7f\tc = %10.7f",t,$itor(a)*SF,$itor(b)*SF,$itor(c)*SF);

    a = 32'b00000000001100000000000000000000; //  1.5
    b = 32'b11111111111100000000000000000000; // -0.5;
    #100; t = $time;
    $fdisplay(write_data, "Tiempo: %t\ta = %10.7f\tb = %10.7f\tc = %10.7f",t,$itor(a)*SF,$itor(b)*SF,$itor(c)*SF);

    // Cerrar archivo de salida
    $fclose(write_data);

    // Final de simulacion
    $display("Test completed");
    //$display("a = %2d, b = %2d, result = %2d", a, b, c);  

  end

endmodule